1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and in particular to a nonvolatile semiconductor memory device having a page mode for simultaneously writing a plurality of data into a plurality of memory cells, respectively.
2. Description of the Background Art
FIG. 5 shows an erasing method (operation) of a DINOR (Divided Bit Line NOR) type flash memory, which will be referred to as a DINOR flash memory and will be described below as an example of a nonvolatile semiconductor memory device in the prior art. FIG. 6 shows a writing method (operation) of the DINOR flash memory which will be described below as an example of the nonvolatile semiconductor memory device in the prior art. Referring to FIGS. 5 and 6, a memory cell of the DINOR flash memory include a P-type well 39, an N.sup.+ layer 27 formed at the surface of P-well 39 and serving as a drain, an N.sup.+ layer 29 formed at the surface of P-well 39 and serving as a source, a floating gate 35 formed on P-well 39 with a gate oxide film (not shown) therebetween, and a control gate 33 formed on floating gate 35 with an insulating film (not shown) therebetween. The memory cell having the above structure are generally called a stacked gate memory cells. The memory cell may be called a "memory cell transistor" in some cases.
A select transistor includes a P-well 39, N.sup.+ layers 27 and 31 formed on P-well 39, and a select gate 37 formed on P-well 39 with a gate oxide film (not shown) therebetween. P-well 39 is formed at a surface of an N-well 41 formed at a main surface of a P-type semiconductor substrate 43. Each of blocks BLK0 and BLK1 includes two memory cells, one select transistor, a main bit line MBL and a sub-bit line SBL. For the sake of illustration, FIGS. 5 and 6 each show two blocks BLK0 and BLK1, each of which includes two memory cells. In practice, however, the blocks are more than two in number, and each block includes more than two memory cells.
The memory cell has a two-layer structure as described above. The gate oxide film under floating gate 35 forming the first layer is a thin film of about 100 .ANG. in thickness. Erasing is performed by injecting electrons into floating gate 35. Writing is performed by removing electrons from floating gate 35. When floating gate 35 contains electrons injected thereinto, the memory cell transistor has a high threshold, and thus does not allow current flow. When electrons are removed from floating gate 35, the memory cell transistor has a low threshold, and allows current flow. A sense amplifier (not shown) reads this difference in current as information of 1/0.
The bit lines are divided into main bit line MBL and sub-bit line SBL. Main bit line MBL and sub-bit line SBL can be isolated by the select transistor. The select transistor also serves to isolate the blocks.
Referring to FIG. 5, an erasing method will be described below. Erasing is performed a block at a time. Block BLK0 is selected, and block BLK1 is not selected. A high voltage of about 12 V is applied to control gates 33 of all the memory cells in selected block BLK0. Thus, a high voltage of about 12 V is applied to word lines (not shown) connected to control gates 33 of all the memory cells in selected block BLK0. A negative voltage of about -11 V is applied to N.sup.+ layers 29, i.e., sources of all the memory cells in selected block BLK0. A negative voltage of about -11 V is applied to P-well 39. By this application of the voltages, a high voltage higher than 20 V is applied across the word line (control gate 33) and P-well 39 in each memory cell of the selected block BLK0. Therefore, electrons are injected into floating gate 35 of the memory cell in selected block BLK0 owing to a tunneling phenomenon.
Control gates 33 of all the memory cells in unselected block BLK1 is at a potential of 0 V. Thus, the word lines (not shown) connected to control gates 33 of all the memory cells in unselected block BLK1 are at a potential of 0 V. N.sup.+ layers 29, i.e., sources of all the memory cells in unselected block BLK1 are at a potential of 0V. Therefore, a tunneling phenomenon does not occur at unselected block BLK1. In selected block BLK0, a voltage of -11 V is applied to select gates 37. In unselected block BLK1, select gate 37, N-well 41 and the P-type semiconductor substrate are at a potential of 0 V. Main bit line MBL is floated.
In selected block BLK0 shown in FIG. 6, a voltage of 12 V is applied to main bit line MBL, and a voltage of 12 V is applied to select gate 37 of the select transistor. Also, in selected block BLK0, a voltage of -11 V is applied to the selected word line. Thus, a voltage of -11 V is applied to control gate 33 connected to the selected word line. By this application of the voltages, electrons tunnels from floating gate 35 of the selected memory cell in selected block BLK0. Removal of electrons can be prevented by setting the potential on main bit line MBL to 0 V. This enables storage of information of 1/0.
FIG. 7 is a schematic block diagram showing a whole structure of a DINOR flash memory which is an example of the nonvolatile semiconductor memory device in the prior art. Portions similar to those in FIG. 5 bear the same reference characters, and will not be described below. Referring to FIG. 7, the DINOR flash memory in the prior art includes a write/erase control circuit 47, source decoders 49 and 51, a select gate decoder group 53, a data I/O buffer 55, sense amplifiers 57, a data driver 59, a Y-gate 60, blocks BLK0 and BLK1, a column latch circuit group 63, a well potential generating circuit 65, a Y-decoder 75, an X-decoder group 77, a high voltage generating circuit 79, a negative voltage generating circuit 81, switching circuits 67, 69, 71 and 73, an address buffer 83 and a verify voltage generating circuit 85.
Y-gate 60 includes a PMOS transistor 91, an NMOS transistor 93 and an inverter 87. PMOS transistor 91 and NMOS transistor 93 form a transfer gate. The transfer gate having the above structure is generally called a complementary (CMOS) transfer gate.
Blocks BLK0 and BLK1 are formed on the same P-well 39. Each of blocks BLK0 and BLK1 includes memory cells MC, select transistors SG, word lines WL, sub-bit lines SBL and main bit lines MBL. Memory cell MC and select transistor SG are the same as the stacked gate memory cell and the select transistor already described with reference to FIG. 5, respectively.
Source decoder 49 corresponds to block BLK0. Source decoder 51 corresponds to block BLK1. Select gate decoder group 53 includes two select gate decoders (not shown), which correspond to two blocks BLK0 and BLK1, respectively. X-decoder group 77 includes two X-decoders (not shown), which correspond to two blocks BLK0 and BLK1, respectively. Column latch circuit group 63 includes two latch circuits (not shown), which correspond to two main bit lines MBL, respectively.
A control gate of memory cell MC is connected to word line WL. A source of memory cell MC in block BLK0 is connected to source decoder 49. A source of memory cell MC in block BLK1 is connected to source decoder 51. A drain of memory cell MC is connected to sub-bit line SBL. A select gate of select transistor SG is connected to select gate decoder group 53. One of source/drain of select transistor SG is connected to sub-bit line SBL, and the other is connected to main bit line MBL. Column latch circuit group 63 is provided for temporarily storing data to be written into memory cell MC. Data input into column latch circuit group 63 is performed by data driver 59 arranged at column side. Well potential generating circuit 65 controls a potential on P-well 39. Sense amplifier 57 reads data from memory cell MC. Y-decoder 75 selects main bit line MBL. Verify voltage generating circuit 85 supplies to the word line a voltage (verify voltage) different from an ordinary read voltage in order to check whether or not electrons are removed to attain a predetermined threshold during writing of data into memory cell MC.
High voltage generating circuit 79 supplies a high voltage to select gate decoder group 53 and column latch circuit group 63, when switching circuit 67 is on. For example, high voltage generating circuit 79 supplies a high voltage to select gate decoder group 53 when writing data into memory cell MC. Further, high voltage generating circuit 79 supplies a high voltage to X-decoder group 77 when switching circuit 69 is on. For example, high voltage generating circuit 79 supplies a high voltage to X-decoder group 77 during an erase operation. Negative voltage generating circuit 81 supplies a negative voltage to well potential generating circuit 65, source decoders 49 and 51, and select gate decoder group 53 when switching circuit 71 is on. For example, negative voltage generating circuit 81 supplies a negative voltage to well potential generating circuit 65, select gate decoder group 53, and source decoders 49 and 51 during the erase operation. Further, negative voltage generating circuit 81 supplies a negative voltage to X-decoder group 77 when switching circuit 73 is on. For example, negative voltage generating circuit 81 supplies a negative voltage to X-decoder group 77 during data writing into memory cell MC.
Write/erase control circuit 47 controls operations of writing data into memory cell MC and erasing data thereof. X-decoder group 77 selects word line WL. Source decoder 49 supplies a negative voltage to the source of memory cell transistor MC, when block BLK0 is selected and data of memory cell MC in block BLK0 is to be erased. Source decoder 51 operates similarly to source decoder 49. Source gate decoder group 53 supplies a negative voltage to the select gate of select transistor SG in the selected block for the erase operation, and supplies a high voltage to the same for the write operation.
For the sake of illustration, FIG. 7 shows two blocks, each including four memory cells. In practice, however, more than two blocks are arranged, and each block includes more than four memory cells. Also, more main bit lines, sub-bit lines and word lines are arranged correspondingly to the number of memory cells.
In some of flash memories, a latch circuit is arranged for each bit line. These latch circuits temporarily store a large number of write data for simultaneously writing these large number of write data in parallel into a large number of memory cells, respectively.
FIG. 8 shows data loading into latch circuits which are provided correspondingly to bit lines in a conventional DINOR flash memory, respectively. Referring to FIG. 8, the conventional DINOR flash memory includes memory cell arrays MA0-MA7, Y-gates Y0-Y7, buffers BF0-BF7 and input data buses B0-B7. Each of memory cell arrays MA0-MA7 includes bit lines BL0-BLn. Each of memory cell arrays MA0-MA7 is divided into blocks BLK0-BLKm. The conventional DINOR flash memory includes transfer gates TG0-TGn and latch circuits L0-Ln, which are provided correspondingly to bit lines BL0-BLn, respectively. Each of blocks BLK0-BLKm is similar to block BLK0 in FIG. 7. Each of bit lines BL0-BLn is similar to main bit line MBL in FIG. 7. Each of Y gates Y0-Y7 is similar to Y-gate 60 in FIG. 7. Each of buffers BF0-BF7 is similar to data driver 59 in FIG. 7.
Data loading will be described below. All transfer gates TG0-TGn, which are connected to bit lines BL0-BLn provided at memory cell arrays MA0-MA7, are turned on in accordance with load signals DLOAD and /DLOAD. Bit lines BL0 in memory cell arrays MA0-MA7 are selected in accordance with an incoming address signal. Selected bit line BL0 included in memory cell array MA0 receives input data Din0 from corresponding input data bus B0 through corresponding buffer BF0 and Y gate Y0. Input data Din0 sent to selected bit line BL0 included in selected memory cell array MA0 is latched by corresponding latch circuit L0. In this manner, selected bit line BL0 supplies data Din0 to be loaded into latch circuit L0, and writes the same into latch circuit L0, whereby the data is loaded. Loading of data into latch circuits L0, which are connected to selected bit lines BL0 included in memory cell arrays MA1-MA7, is performed in the same manner as the loading of data into latch circuit L0 connected to selected bit line BL0 included in memory cell array MA0. Thus, data are simultaneously loaded into eight latch circuits L0 connected to eight selected bit lines BL0, respectively.
Then, in accordance with the address signals supplied to the memory cell arrays, bit lines BL1 are selected in memory cell arrays MA0-MA7, respectively. Data loading into latch circuits L1 connected to selected bit lines BL1 is performed in the same manner as the data loading into latch circuits L0 described above. Then, in accordance with the incoming address signal, bit lines BL2 are selected in memory cell arrays MA0-MA7, respectively. Data loading into latch circuits L2 connected to selected bit lines BL2 is performed similarly to the data loading into latch circuits L0 described above. In this manner, bit lines BL0-BLn in each of memory cell arrays MA0-MA7 are successively selected in the order from bit line BL0 to bit line BLn, whereby data are loaded into all latch circuits L0-Ln.
FIG. 9 is a circuit diagram showing a specific structure of latch circuit L0 in FIG. 8 and transfer gate TG0. Portions similar to those in FIG. 8 bear the same reference characters, and will not be specifically described below. Referring to FIG. 9, latch circuit L0 includes a clocked inverter 95, and inverters 19 and 21. Inverters 19 and 21 form a latch unit receiving a high voltage Vpp from a power supply 1. Clocked inverter 95 is arranged between bit line BL0 and a node N, and receives write signals WRITE and /WRITE. Transfer gate TG0 is arranged between bit line BL0 and node N, and receives load signals DLOAD and /DLOAD. This transfer gate TG0 is similar to the transfer gate in FIG. 7 formed of PMOS transistor 91 and NMOS transistor 93. A PMOS transistor (not shown) forming transfer gate TG0 receives load signal /DLOAD on its gate, and NMOS transistor (not shown) forming transfer gate TG0 receives load signal DLOAD on its gate. Latch circuits L1-Ln and transfer gates TG1-TGn have the same structures as latch circuit L0 and transfer gate TG0.
FIG. 10 is a circuit diagram showing a specific structure of clocked inverter 95 in FIG. 9. Portions similar to those in FIG. 9 bear the same reference characters, and will not be described below. Referring to FIG. 10, the clocked inverter is formed of PMOS transistors 97 and 99, and NMOS transistors 101 and 103. Referring to FIGS. 9 and 10, when data is to be loaded into latch circuit L0 in memory cell array MA0 (FIG. 8), transfer gate TG0 is turned on to connect bit line BL0 to node N. Data Din0 received on bit line BL0 is latched by the latch unit formed of inverters 19 and 21. In the data load operation, write signal /WRITE is at H-level, and write signal WRITE is at L-level. When data loaded into latch circuit L0 is to be written into the memory cell (not shown), transfer gate TG0 is turned off. Clocked inverter 95 is supplied with write signal /WRITE at L-level and write signal WRITE at H-level. Thereby, data loaded into latch circuit L0 is applied onto bit line BL0.
In the conventional DINOR flash memory, the latch circuit connected to the bit line corresponding to the selected address is supplied with data from the bit line corresponding to the selected address as described above, whereby data loading is performed. Thus, address information and data are merged at the bit line itself, and data to be loaded into the latch circuit is latched through the transfer gate arranged corresponding to the latch circuit. Therefore, many bit lines are charged with electric charges, when data are loaded into all latch circuits L0-Ln connected to bit lines BL0-BLn in memory cell arrays MA0-MA7. As one of functions of the flash memory, there is a mode in which data is read from the memory cell array immediately after data loading. In this mode, a reading speed is disadvantageously reduced due to electric charges charged onto the many bit lines. In the data load operation, all transfer gates TG0-TGn connected to bit lines BL0-BLn in memory cell arrays MA0-MA7 are on. Therefore, the bit lines connected to the latch circuits of which data loading is completed must keep the charged electric charges until data loading into other latch circuits is completed.
As another function of the flash memory, there is a mode in which data loading is effected on only a part of latch circuits, and data loading will be effected on the other latch circuits after processing such as reading of data from the memory cell array. In this case, even when data loading is to be effected on only a part of latch circuits, all transfer gates TG0-TGn connected to bit lines BL0-BLn in memory cell arrays MA0-MA7 are turned on. When data loading is to be performed later, therefore, the latch circuits of which data loading is already completed are connected to the bit lines. As a result, data of the latch circuits of which data loading is already completed may be destroyed due to floating capacities of the bit lines.
In the conventional DINOR flash memory, data is loaded into the latch circuit by forcedly inverting the latch circuit. Therefore, a potential having a sufficiently large drive power must be supplied to the bit line. Therefore, Y-gates Y0-Y7 must use complementary (CMOS) transfer gates. This results in a problem of increasing a circuit area.